Pilz PSEN enc s2 eCAM - Handbuch (Seite 84)

Installation / Preparation for commissioning
Pilz GmbH & Co. KG, Felix-Wankel-Straße 2, 73760 Ostfildern, Deutschland
Telefon +49 711 3409-0, Telefax +49 711 3409-133, E-Mail: [email protected]
35
English
5.8 SSI interface
NOTICE
Risk of damage to subsequent electronics due to
overvoltages caused by a missing earth reference
point!
• If the earth reference point is missing entirely, e.g. 0 V
of the power supply is not connected, voltages equal
to the level of the supply voltage can occur at the
outputs of this interface.
• An earth reference point must be guaranteed to be
present at all times.
In the rest condition, Data+ and Clock+ are high. This corresponds to the time before
Point
(1) in the diagram below.
The first time the clock signal changes from high to low (1) , the internal retriggerable
monoflop is set with the monoflop time t
M
.
The time t
M
determines the lowest transmission frequency (T = t
M
/ 2). The upper cut-
off frequency is calculated from the sum of all the signal run times and is also limited
by the built-in filter circuits.
With each additional falling clock edge, the active status of the monoflop is extended
by the time t
M
; this is the case by Point (4) at the latest.
By setting the monoflop (1) , the bit-parallel data present on the internal parallel-serial
converter is stored in an input latch of the shift register via an internally generated
signal. This ensures that the data does not change as the position value is
transmitted.
The first time the clock signal changes from low to high
(2) , the most significant bit
(MSB) of the device information is connected to the serial data output. With each
additional rising edge, the next lower value bit is moved to the data output.
When the clock sequence is complete, the data lines are held at 0 V (Low) for the
duration of the monoperiod t
M
(4) . This is also used to calculate the minimum pause time
t
p
that must be maintained between two consecutive pulse sequences and amounts to 2 *
t
M
.
The data is read in by the evaluation electronics from the first rising clock edge. Based
on various factors, a delay time of t
V
>100 ns results, without cable. As a result, the
measuring system moves the data to the output after the delay time t
V
. For this reason,
a “Pause-1” is read in at Point (2) . This must be rejected or can be used in conjunction
with a “0” after the LSB data bit for open circuit monitoring. The MSB data bit is not
read in until Point
(3) . For this reason, the number of clock pulses must always be one
higher (n+1) than the number of data bits to be transmitted.